Heretofore, the item described in Patent Document 1 has been known as a PLL frequency synthesizer. FIG. 1 is a block diagram showing the configuration of a conventional PLL frequency synthesizer. In this drawing, a plurality of PLL circuits 10-1 through 10-n having loop filters with different cutoff frequencies, provided in parallel with respect to an input signal, each output an oscillation signal phase-synchronized with the input signal. Specifically, to take the example of PLL circuit 10-1, the input signal is subjected to phase comparison by a phase comparator 11 with an oscillation signal output from a voltage controlled oscillator 13, and the comparison result is output to voltage controlled oscillator 13 via a loop filter 12, and is also output to a lock monitor 20.
Based on the comparison results output from the phase comparators of the PLL circuits, lock monitor 20 detects locked PLL circuits, and a control circuit 30 selects one PLL circuit from among the PLL circuits detected as locked based on a variable condition, and controls a switch 40, enabling the output signal (oscillation signal) of the selected PLL circuit to be obtained.
Here, conditions for PLL circuit selection by control circuit 30 include a case in which the PLL circuit having the loop filter with the highest cutoff frequency is selected, and a case in which the PLL circuit having the loop filter with the lowest cutoff frequency is selected. When the PLL circuit having the loop filter with the highest cutoff frequency is selected, the PLL frequency synthesizer can achieve improvement of near C/N and shortening of lockup time. On the other hand, when the PLL circuit having the loop filter with the lowest cutoff frequency is selected, the PLL frequency synthesizer can reduce residual FM, which is a frequency fluctuation component. Near C/N means C/N in the vicinity of the output spectrum of a voltage controlled oscillator. Residual FM represents the amount of frequency fluctuation of a voltage controlled oscillator within a short time, and can be measured with a modulation analyzer.
Thus, with a conventional PLL frequency synthesizer, a plurality of PLL circuits have loop filters with different cutoff frequencies, and an oscillation signal corresponding to the characteristics required by the system can be obtained by switching the loop filter.
Sample loop filter configurations are shown in FIG. 2 and FIG. 3. FIG. 2 shows a sample configuration of a second-order loop filter, and FIG. 3 shows a sample configuration of a lag-lead filter.    Patent Document 1: Unexamined Japanese Patent Publication No. 2001-292059